FIG. 1 illustrates a prior art voltage level shifter circuit. A differential input signal is applied to input ports 102 and 104, and the output signal is taken at output ports 106 and 108. The level shifter circuit is designed to shift input voltage levels VSSL and VCCL to output voltage levels VSSH and VCCH. The voltage levels VSSL and VCCL are the LOW and HIGH voltages, respectively, in a first voltage domain; and the voltage levels VSSH and VCCH are the LOW and HIGH voltages, respectively, in a second voltage domain, where VSSL<VSSH and VCCL<VCCH. The voltage VCCL is provided by diode-connected pMOSFETs 110 and 112, with their drains connected to their respective gates, to provide a voltage drop (buffer) of VT, where VT denotes their threshold voltage. For the circuit of FIG. 1, VT+VSSL=VSSH. Cross-coupled transistors 114 and 116 provide a differential latch amplifier function so that either output port 106 or 108 is brought to VCCH, depending upon the input signals at input ports 102 and 104.
In many instances, pMOSFETs 110 and 112 may have a relatively high leakage current, so that to maintain the voltage buffer VT provided by these diode-connected transistors, pMOSFETs 130 and 132 are introduced to provide leakage current to the sources of diode-connected pMOSFETs 110 and 112. However, this intentionally introduced leakage current contributes to static power consumption. Reducing the leakage current by decreasing the size of diode-connected transistors 110 and 112 may aggravate the dynamic behavior of the circuit. Furthermore, the voltage buffer provided by transistors 110 and 112, as well as their leakage currents, may change across process corners. Note also that when in a static mode, there is a direct current path from power supply rail (VCCH) 134 to one of power supply rails 136 (VCCL), thereby also contributing to static power consumption.